As technology continues to scale into the sub-micron realm, applications move toward higher frequencies and higher levels of integration such that parasitic effects from interconnect wiring significantly affect integrated circuit performance. For example, the parasitic effects from interconnect wiring play an important role in timing, power, gain, matching network, reliability, and noise performance of the integrated circuit such that the parasitic effects from interconnect wiring can no longer be ignored or the integrated circuit may fail.
Specifically, one of the challenges faced by submicron integrated circuit designers is the issue of parasitic effects from the interconnect wiring between a semiconductor die or chip and a chip package, e.g., chip-package coupling. More specifically, the interaction between a semiconductor die or chip when packaged using flip chip technology can cause a significant parasitic coupling effect between the chip and the package due to the fact that the chip and package (solder bumps and the first package metal layer) are located in very close proximity. A chip is semiconductor material, e.g., silicon, in which an integrated circuit is formed, and a chip package is the substrate upon which the chip, or chips, is mounted, e.g., a ceramic laminate package, or printed circuit board. The chip package provides a means of connecting the internal chip components to external circuitry. The chip-package coupling has become a major factor in successfully predicting performance of the integrated circuit on the chip.
In order to take parasitic effects from interconnect wiring into consideration during post layout analysis of an integrated circuit, it is necessary to create electrical models for the physical connections present between the various devices in the integrated circuit design. This process is typically known as parasitic extraction (PEX). However, traditional PEX methodologies only capture chip level couplings and by default assume a mounted package without taking into account mutual coupling effects between the chip and the chip package.
Common practice in order to take into account the chip-package coupling in predicting performance of an integrated circuit includes using an electromagnetic (EM) simulator to model chip package effects and to evaluate the chip-package coupling. However, EM simulation capability is limited by the complexity of interconnect wiring structures. Additionally, package metal routing is commonly modeled by 3-D EM tools, while chip-level parasitics are usually modeled by EDA PEX tools. The integration of an EM model netlist derived from 3-D EM tools and an on chip parasitic netlist derived from EDA PEX tools into simulations is typically a challenge due to different formats from tool vendors, interface restrictions, etc. Furthermore, stand-alone models of chip packages do not take into account mutual coupling effects between the chip and the chip package.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.